1. Field of Invention
The present invention relates to a circuit substrate used for an electro-optical device, such as a display panel or the like. More particularly, the invention relates to a configuration to enhance the reduction or prevention of electrostatic breakdown during manufacturing or operating of the circuit substrate.
2. Description of Related Art
With some related art circuit substrates used for electro-optical devices, such as active-matrix-driven liquid crystal display panels, EL (electro-luminescence) display panels, or the like, an electrostatic-protection configuration can be provided to reduce or prevent breakdown of the internal circuit due to static electricity occurring during manufacturing or operation.
Related art electrostatic-protection configurations, can be provided such that terminals are connected with protection patterns with the adjacent terminals short-circuited or connected with a resistance during manufacturing, and the protection patterns are cut off following completion, as disclosed in Japanese Unexamined Patent Application Publication No. 58-116573 or Japanese Unexamined Patent Application Publication No. 63-106788. The related art also includes a structure where all the disposed terminals are short-circuited along the perimeter of the substrate outward from the disposed terminals during manufacturing, as disclosed in Japanese Unexamined Patent Application Publication No. 2-242229, Japanese Unexamined Patent Application Publication No. 7-181516, and Japanese Unexamined Patent Application Publication No. 7-175086.
Other related art electrostatic protection configurations can be provided such that resistances in the range causing no problem with regard to operation of the data lines and the scan lines are added, and accordingly, a step of cutting off the protection patterns can be eliminated even following electrical testing, and electrostatic breakdown can also be reduced or prevented in the final product, as disclosed in Japanese Unexamined Patent Application Publication No. 63-085586, Japanese Unexamined Patent Application Publication No. 2-061618, Japanese Unexamined Patent Application Publication No. 6-273783, and Japanese Unexamined Patent Application Publication No. 8-179360.